1. Field of the Invention
The present invention relates to memories in which data can be refreshed such, for example, as memories which use "volatile" storage cells of the MOS type (Metal, Oxide, Semiconductor) in which the levels of electrical charge, by an agreed convention, represent the "0" and "1" values of the binary digits which they store.
The invention relates more particularly to those memories of this kind which are, a priori, divided into two half-memories having equal data capacities, each half-memory containing the same number of columns having the same digit capacities. Each column is bisected at the center by a refreshing amplifier and the digit storing cells can be connected to the resulting half-columns for writing, reading (followed by rewriting) and refreshing.
2. Description of the Prior Art
In a memory of this kind, a pair of buses for reading (followed by rewriting since the reading process destroys the data read) is situated between two half-memories. Each bus can be connected to the columns of the half-memory by means of an equal number of addressable switch elements. All connections are made on one side of the refreshing amplifier. Thus, any connection between one of the buses and a column is made by connecting the bus concerned to one of the half-columns.